The present invention relates to a semiconductor integrated amplifier circuit integrated in a single semiconductor substrate and, more particularly, to an amplifier circuit and an oscillation circuit making use of CMOS (Complementary MOS).
Such an oscillation circuit has been known as having a CMOS amplifier circuit incorporating a p-channel MISFET and an n-channel MISFET are connected in series, so as to perform a complementary operation upon common application of an input signal to the gates of both MISFETs.
A power-saving CMOS amplifier circuit as shown in FIG. 1 has been proposed by Osamu Yamashiro, one of the present inventors, in U.S. Patent Application Ser. No. 719,238 now U.S. Pat. No. 4,100,502, issued July 11, 1978 and herein incorporated by reference. In this CMOS amplifier circuit, as shown in FIG. 1, a p-channel FETMP provided at the side of one power source terminal VDD and an n-channel FETMN provided at the side of the other power source terminal VSS are connected to each other through a load resistance RL. At the same time, bias resistances RF1 and RF2 are connected between the gates and drains of a respective one of the FETMP and FETMN. Further, a capacitor CO for blocking DC current is connected between the gates of both FETs.
In this amplifier circuit, since the inverter constituted by complementary MOSFET is provided with the load resistance RL, it is possible to make the input/output transmission characteristic steep enough, by selecting the resistance value of the load resistance larger than the resistance between the source and drain of each of the insulated gate type field effect transistor MP, MN. At the same time, by doing so, the bias voltage between the gate and the source comes close to its threshold, so that the power consumption is considerably decreased.
In addition, the bias resistances RF1 and RF2 connected between the gate and the drain of respective FETs (FETMP and FETMN) function to bias the potentials of respective gates to a level substantially equal to the DC potential of respective drains. The biasing point is more stabilized, and a higher mu-factor is maintained, as the values of the resistances becomes smaller. This amplifier circuit makes the most of these phenomena.
Further, in the above stated circuit, the DC component of the input signal applied to the terminal IN is cut by the DC blocking capacitor CO, so that the bias points of FETMP and FETMN are determined independently, without being affected by each other.
Consequently, an amplification circuit having a high stability and capable of greatly saving the power is obtained.
By the way, it is preferable that the electronic devices consisting of various circuits have a reduced number of parts. To cope with this demand, the present inventors have made various studies and attempts to obtain an amplifier of so-called semiconductor integrated circuit device type, in which the amplifier is composed in a single semiconductor substrate. As a result of these studies, the inventors have confirmed that the resistances RL, RF1 and RF2 can be made integral with other P and N type MOSFETs in a single semiconductor chip, by making use of resistors separated by PN junctions from the semiconductor substrate, the resistors consisting of a polysilicon body or FET resistors consisting of the resistance produced between the source and drain of a MOSFET when a fixed voltage is applied to the MOSFET.
The inventors have further attempted to integrate the DC current blocking capacitor CO in the above stated circuit. The first attempt was to obtain the integrated capacitor CO from a so-called MIS capacitor having a first electrode constituted by a semiconductive region on the surface of a semiconductor substrate and a second electrode constituted by a conductive layer formed on the semiconductive region with an insulating film disposed therebetween. However, this arrangement has proven to have a disadvantage in that the function of the amplifier circuit is adversely affected seriously by a so-called parasitic capacitance CX caused by a PN junction between the semiconductive region forming one of the electrodes of the MIS capacitor and the substrate of an opposite conductive type to the semiconductive region. Namely, the signal transfer characteristics of the amplifier is largely affected by the position at which the parasitic capacitance is disposed equivalently, in connection with the input terminal to which the input signal is delivered.
Further, in a quartz oscillator or the like device making use of this type of amplifier, when a parasitic capacitance of a capacitance value matching that of a capacitor, which is connected externally of the IC for the purpose of adjustment of the oscillation frequency, is provided in the positive feedback circuit, the adjustable range of the frequency is largely narrowed due to the presence of the parasitic capacitance CX.
Especially, in such electronic devices as electronic timepieces which requires not only a reduced power consumption but also a highly precise circuit operation, the above stated defect causes a fatal problem which would hinder or limit the future incorporation of such an integrated circuit in these devices.